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[VHDL-FPGA-Verilog] utopia DL : 0: utopia，system verilog写的CPU测试平台代码-utopia, system verilog code written in CPU test platform
Date : 2025-07-16 Size : 16kb User : 磊
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Date : 2025-07-16 Size : 4.72mb User : 石
[VHDL-FPGA-Verilog] SinglecycleCPU DL : 0: 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
Date : 2025-07-16 Size : 26kb User : Matgek
[VHDL-FPGA-Verilog] _8259A DL : 0: 　 8259A是专门为了对8085A和8086/8088进行中断控制而设计的芯片，它是可以用程序控制的中断控制器。单个的8259A能管理8级向量优先级中断。在不增加其他电路的情况下，最多可以级联成64级的向量优先级中断系统。8259A有多种工作方式，能用于各种系统。各种工作方式的设定是在初始化时通过软件进行的。在总线控制器的控制下,8259A芯片可以处于编程状态和操作状态.编程状态是CPU使用IN或OUT指令对8259A芯片进行初始化编程的状态- 8259A is designed to be on the 8085A and 8086/8088 designed to interrupt control chip, which is the interrupt controller can be programmed. 8259A can manage a single priority interrupt vector 8. Without increasing the other circuit cases, up to 64-level cascaded priority interrupt system vector. 8259A there are several methods of work, can be used in a variety of systems. A variety of work settings is carried out by software initialization. Under the control of the bus controller, 8259A chip can be programmed at the state and operating state. Programming state is CPU use IN or OUT instruction program on the 8259A chip, to initialize the state of
Date : 2025-07-16 Size : 747kb User : keven
[VHDL-FPGA-Verilog] LCD12864_ST7920 DL : 0: LCD12864驱动程序可实现以ARM为CPU的LCD12864的驱动-LCD12864 driver enables ARM-CPU of LCD12864 drive
Date : 2025-07-16 Size : 51kb User : 陈锴
[VHDL-FPGA-Verilog] risc8 DL : 0: verilog risc8 cpu-verilog risc8 cpu
Date : 2025-07-16 Size : 423kb User : 谭腾飞
[VHDL-FPGA-Verilog] uart DL : 0: UART verilog 代码，内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
Date : 2025-07-16 Size : 15kb User : dingyy
[VHDL-FPGA-Verilog] i2c DL : 0: I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
Date : 2025-07-16 Size : 13kb User : dingyy
[VHDL-FPGA-Verilog] alu DL : 0: this is source code in verilog for arithmatic logic unit for RISC cpu
Date : 2025-07-16 Size : 62kb User : Harshit B J
[VHDL-FPGA-Verilog] RISCcpu DL : 1: this verilog model of RISC CPU-this is verilog model of RISC CPU
Date : 2025-07-16 Size : 138kb User : Harshit B J
[VHDL-FPGA-Verilog] F10-Single-Cycle-MIPS DL : 0: This a verilog code of single cycle mips-This is a verilog code of single cycle mips
Date : 2025-07-16 Size : 574kb User : hualin
[VHDL-FPGA-Verilog] CPU DL : 0: 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
Date : 2025-07-16 Size : 5.32mb User : Po
[VHDL-FPGA-Verilog] cpu DL : 0: 简单的cpu，以verilog语言写的，希望大家能提点意见。-Simple cpu, the verilog language to write, and I hope we can Tidianyijian.
Date : 2025-07-16 Size : 78kb User : 书柬图章
[VHDL-FPGA-Verilog] cpu DL : 0: 本程序主要完成cpu的几个主功能模块的开发，开发语言为verilog硬件语言，基本能模拟cpu的核心功能！-The program mainly to complete the main features of several cpu module development, hardware development language for the verilog language, the basic core functionality can simulate the cpu!
Date : 2025-07-16 Size : 5kb User : 赵洵
[VHDL-FPGA-Verilog] CPU DL : 0: mips系列，CPU的Verilog语言设计，自己写的-mips series, CPU of the Verilog language design, to write their own
Date : 2025-07-16 Size : 4kb User : ysshr
[VHDL-FPGA-Verilog] NET2 DL : 0: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Date : 2025-07-16 Size : 1.77mb User : sansfroid
[VHDL-FPGA-Verilog] LIP3001CORE_cpu DL : 0: CPU Verilog Module source code
Date : 2025-07-16 Size : 159kb User : jc
[VHDL-FPGA-Verilog] risc_cup DL : 0: 精简指令集CPU的VERILOG语言实现，很有用-RISC CPU the VERILOG language, very useful
Date : 2025-07-16 Size : 463kb User : 侯勇
[VHDL-FPGA-Verilog] DW8051_core DL : 0: 8051的内核源码,用verilog HDL写成，已验证功能正确-open core fo 8051 cpu
Date : 2025-07-16 Size : 428kb User : gaoming
[VHDL-FPGA-Verilog] CPU DL : 0: cup developed by scope verilog
Date : 2025-07-16 Size : 9kb User : wei chenghao

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